C8051F388 Datasheet, PDF (164/285 Pages) –

C8051F388/9/A/B
SFR Definition 20.20. P4: Port 4
Bit
7
6
5
4
3
2
1
0
Name
P4[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xC7; SFR Page = All Pages
Bit Name
Description
7:0 P4[7:0] Port 4 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Read
0: P4.n Port pin is logic
LOW.
1: P4.n Port pin is logic
HIGH.
SFR Definition 20.21. P4MDIN: Port 4 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P4MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF5; SFR Page = All Pages
Bit
Name
Function
7:0 P4MDIN[7:0] Analog Configuration Bits for P4.7–P4.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P4.n pin is configured for analog mode.
1: Corresponding P4.n pin is not configured for analog mode.
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Rev. 1.1