C8051F388 Datasheet, PDF (8/285 Pages) –

C8051F388/9/A/B
List of Figures
Figure 1.1. C8051F388/A Block Diagram ................................................................ 17
Figure 1.2. C8051F389/B Block Diagram ................................................................ 18
Figure 3.1. TQFP-48 (C8051F388/A) Pinout Diagram (Top View) .......................... 24
Figure 3.2. TQFP-48 Package Diagram .................................................................. 25
Figure 3.3. TQFP-48 Recommended PCB Land Pattern ........................................ 26
Figure 3.4. LQFP-32 (C8051F389/B) Pinout Diagram (Top View) .......................... 27
Figure 3.5. LQFP-32 Package Diagram .................................................................. 28
Figure 3.6. LQFP-32 Recommended PCB Land Pattern ........................................ 29
Figure 3.7. QFN-32 (C8051F389/B) Pinout Diagram (Top View) ............................ 30
Figure 3.8. QFN-32 Package Drawing .................................................................... 31
Figure 3.9. QFN-32 Recommended PCB Land Pattern .......................................... 32
Figure 4.1. Connection Diagram with Voltage Regulator Used ............................... 33
Figure 4.2. Connection Diagram with Voltage Regulator Not Used ........................ 33
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 42
Figure 6.2. Typical Temperature Sensor Transfer Function .................................... 44
Figure 6.3. Temperature Sensor Error with 1-Point Calibration .............................. 45
Figure 6.4. 10-Bit ADC Track and Conversion Example Timing ............................. 47
Figure 6.5. ADC0 Equivalent Input Circuits ............................................................. 48
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 54
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 54
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 58
Figure 8.1. Comparator0 Functional Block Diagram ............................................... 60
Figure 8.2. Comparator1 Functional Block Diagram ............................................... 61
Figure 8.3. Comparator Hysteresis Plot .................................................................. 62
Figure 8.4. Comparator Input Multiplexer Block Diagram ........................................ 67
Figure 11.1. CIP-51 Block Diagram ......................................................................... 75
Figure 13.1. On-Chip Memory Map for 64 kB Devices (C8051F388/9) ................... 85
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F38A/B) .................. 86
Figure 14.1. Multiplexed Configuration Example ..................................................... 92
Figure 14.2. Non-multiplexed Configuration Example ............................................. 93
Figure 14.3. EMIF Operating Modes ....................................................................... 94
Figure 14.4. Non-Multiplexed 16-bit MOVX Timing ................................................. 98
Figure 14.5. Non-Multiplexed 8-bit MOVX without Bank Select Timing .................. 99
Figure 14.6. Non-Multiplexed 8-bit MOVX with Bank Select Timing ..................... 100
Figure 14.7. Multiplexed 16-bit MOVX Timing ....................................................... 101
Figure 14.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 102
Figure 14.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 103
Figure 17.1. Reset Sources ................................................................................... 123
Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 124
Figure 18.1. Flash Program Memory Map and Security Byte ................................ 131
Figure 19.1. Oscillator Options .............................................................................. 136
Figure 19.2. External Crystal Example .................................................................. 144
Figure 20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 147
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Rev. 1.1