C8051F388 Datasheet, PDF (35/285 Pages) –

C8051F388/9/A/B
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Test Condition
Min Typ Max Unit
Digital Supply Voltage
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)¹
V_RST 3.3 3.6
V
— 1.5 —
V
0
— 48 MHz
Specified Operating
Temperature Range
–40 — +85 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
I_DD2
SYSCLK = 48 MHz, V_DD = 3.3 V
— 12 14 mA
SYSCLK = 24 MHz, V_DD = 3.3 V
—
7
8 mA
SYSCLK = 1 MHz, V_DD = 3.3 V
— 0.45 0.85 mA
SYSCLK = 80 kHz, V_DD = 3.3 V
— 280 — μA
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle I_DD2
Digital Supply Current
(Stop or Suspend Mode, shut-
down)
SYSCLK = 48 MHz, V_DD = 3.3 V
SYSCLK = 24 MHz, V_DD = 3.3 V
SYSCLK = 1 MHz, V_DD = 3.3 V
SYSCLK = 80 kHz, V_DD = 3.3 V
Oscillator not running (STOP mode),
Internal Regulators OFF, V_DD = 3.3 V
Oscillator not running (STOP or SUS-
PEND), REG0 and REG1 both in low
power mode, V_DD = 3.3 V.
Oscillator not running (STOP or SUS-
PEND), REG0 OFF, V_DD = 3.3 V.
— 6.5 8 mA
— 3.5 5 mA
— 0.35 — mA
— 220 — μA
—
1
— μA
— 100 — μA
— 150 — μA
Notes:
1. SYSCLK must be at least 32 kHz to enable debugging.
2. Includes normal mode bias current for REG0 and REG1. Does not include current from internal oscillators or
other analog peripherals.
Rev. 1.1
35