C8051F388 Datasheet, PDF (176/285 Pages) –

C8051F388/9/A/B
SFR Definition 21.4. SMB0CN: SMBus Control
Bit
7
6
5
4
3
2
1
0
Name MASTER0 TXMODE0 STA0
STO0 ACKRQ0 ARBLOST0 ACK0
SI0
Type
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC0; SFR Page = 0; Bit-Addressable
Bit Name
Description
Read
Write
7 MASTER0 SMBus0 Master/Slave
0: SMBus0 operating in N/A
Indicator. This read-only bit slave mode.
indicates when the SMBus0 is 1: SMBus0 operating in
operating as a master.
master mode.
6 TXMODE0 SMBus0 Transmit Mode
0: SMBus0 in Receiver N/A
Indicator. This read-only bit Mode.
indicates when the SMBus0 is 1: SMBus0 in Transmitter
operating as a transmitter. Mode.
5
STA0 SMBus0 Start Flag.
0: No Start or repeated
Start detected.
1: Start or repeated Start
detected.
0: No Start generated.
1: When Configured as a
Master, initiates a START
or repeated START.
4
STO0 SMBus0 Stop Flag.
0: No Stop condition
0: No STOP condition is
detected.
transmitted.
1: Stop condition detected 1: When configured as a
(if in Slave Mode) or
Master, causes a STOP
pending (if in Master
condition to be transmit-
Mode).
ted after the next ACK
cycle.
Cleared by Hardware.
3 ACKRQ0 SMBus0 Acknowledge
Request.
0: No ACK requested
N/A
1: ACK requested
2 ARBLOST0 SMBus0 Arbitration Lost 0: No arbitration error. N/A
Indicator.
1: Arbitration Lost
1 ACK0 SMBus0 Acknowledge.
0: NACK received.
1: ACK received.
0: Send NACK
1: Send ACK
0
SI0 SMBus0 Interrupt Flag.
0: No interrupt pending 0: Clear interrupt, and ini-
This bit is set by hardware 1: Interrupt Pending
tiate next state machine
under the conditions listed in
event.
Table 15.3. SI0 must be
1: Force interrupt.
cleared by software. While SI0
is set, SCL0 is held low and
the SMBus0 is stalled.
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Rev. 1.1