C8051F388 Datasheet, PDF (88/285 Pages) –

C8051F388/9/A/B
14. External Data Memory Interface and On-Chip XRAM
The chip includes 4 kB (C8051F388/9) or 2 kB (C8051F38A/B) of RAM on-chip, and is mapped into the
external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on
the C8051F388/A devices, which can be used to access off-chip data memories and memory-mapped
devices connected to the GPIO ports. The external memory space may be accessed using the external
move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using
R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte
of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in
SFR Definition 14.1). Note: the MOVX instruction can also be used for writing to the FLASH memory. See
Section “18. Flash Memory” on page 129 for details. The MOVX instruction accesses XRAM by default.
14.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
14.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:
MOV DPTR, #1234h
MOVX A, @DPTR
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
14.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
MOV
MOV
MOVX
EMI0CN, #12h
R0, #34h
a, @R0
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
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