C8051F388 Datasheet, PDF (135/285 Pages) –

C8051F388/9/A/B
SFR Definition 18.3. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
Name FOSE
Reserved
FLRT
Reserved
Type R/W
R/W
R/W
R/W
Reset
1
0
0
0
0
0
0
0
SFR Address = 0xB6; SFR Page = All Pages
Bit Name
Function
7
FOSE Flash One-shot Enable.
This bit enables the Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads. At system
clock frequencies below 10 MHz, disabling the Flash one-shot will increase system
power consumption.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
6:5 Reserved Must write 00b.
4
FLRT FLASH Read Time.
This bit should be programmed to the smallest allowed value, according to the system
clock speed.
0: SYSCLK <= 25 MHz.
1: SYSCLK <= 48 MHz.
3:0 Reserved Must write 0000b.
Rev. 1.1
135