C8051F388 Datasheet, PDF (60/285 Pages) –

C8051F388/9/A/B
8. Comparator0 and Comparator1
C8051F388/9/A/B devices include two on-chip programmable voltage comparators: Comparator0 is shown
in Figure 8.1, Comparator1 is shown in Figure 8.2. The two comparators operate identically with the follow-
ing exceptions: (1) Their input selections differ as described in Section “8.1. Comparator Multiplexers” on
page 67; (2) Comparator0 can be used as a reset source.
The Comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 or CP1), or an
asynchronous “raw” output (CP0A or CP1A). The asynchronous signals are available even when the sys-
tem clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “20.2. Port I/O Initialization” on page 152). Comparator0 may also be used as a
reset source (see Section “17.5. Comparator0 Reset” on page 126).
The Comparator inputs are selected by the comparator input multiplexers, as detailed in Section
“8.1. Comparator Multiplexers” on page 67.
Figure 8.1. Comparator0 Functional Block Diagram
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Rev. 1.1