C8051F388 Datasheet, PDF (86/285 Pages) –

C8051F388/9/A/B
Figure 13.2. On-Chip Memory Map for 32 kB Devices (C8051F38A/B)
13.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F388/9/A/B implements 64 or 32 kB
of this program memory space as in-system, re-programmable Flash memory. Note that on the
C8051F388/9 (64 kB version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-
volatile data storage. Refer to Section “18. Flash Memory” on page 129 for further details.
13.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.
Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
bytes or as 128 bit locations accessible with the direct addressing mode.
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Rev. 1.1