C8051F388 Datasheet, PDF (256/285 Pages) –

C8051F388/9/A/B
SFR Definition 25.24. TMR5CN: Timer 5 Control
Bit
7
6
5
4
3
2
1
0
Name TF5H
TF5L TF5LEN
T5SPLIT TR5
T5XCLK
Type R/W
R/W
R/W
R
R/W
R/W
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC8; SFR Page = F; Bit-Addressable
Bit
Name
Function
7
TF5H Timer 5 High Byte Overflow Flag.
Set by hardware when the Timer 5 high byte overflows from 0xFF to 0x00. In 16 bit
mode, this will occur when Timer 5 overflows from 0xFFFF to 0x0000. When the
Timer 5 interrupt is enabled, setting this bit causes the CPU to vector to the Timer 5
interrupt service routine. This bit is not automatically cleared by hardware.
6
TF5L Timer 5 Low Byte Overflow Flag.
Set by hardware when the Timer 5 low byte overflows from 0xFF to 0x00. TF5L will
be set when the low byte overflows regardless of the Timer 5 mode. This bit is not
automatically cleared by hardware.
5 TF5LEN Timer 5 Low Byte Interrupt Enable.
When set to 1, this bit enables Timer 5 Low Byte interrupts. If Timer 5 interrupts are
also enabled, an interrupt will be generated when the low byte of Timer 5 overflows.
4 Unused Read = 0b; Write = don’t care.
3 T5SPLIT Timer 5 Split Mode Enable.
When this bit is set, Timer 5 operates as two 8-bit timers with auto-reload.
0: Timer 5 operates in 16-bit auto-reload mode.
1: Timer 5 operates as two 8-bit auto-reload timers.
2
TR5
Timer 5 Run Control.
Timer 5 is enabled by setting this bit to 1. In 8-bit mode, this bit enables/disables
TMR5H only; TMR5L is always enabled in split mode.
1 Unused Read = 0b; Write = don’t care.
0 T5XCLK Timer 5 External Clock Select.
This bit selects the external clock source for Timer 5. However, the Timer 5 Clock
Select bits (T5MH and T5ML in register CKCON1) may still be used to select
between the external clock and the system clock for either timer.
0: Timer 5 clock is the system clock divided by 12.
1: Timer 5 clock is the external clock divided by 8 (synchronized with SYSCLK).
256
Rev. 1.1