C8051F388 Datasheet, PDF (153/285 Pages) –

C8051F388/9/A/B
SFR Definition 20.1. XBR0: Port I/O Crossbar Register 0
Bit
7
6
5
4
3
2
1
0
Name CP1AE CP1E CP0AE CP0E SYSCKE SMB0E SPI0E URT0E
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE1; SFR Page = All Pages
Bit Name
Function
7 CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1A unavailable at Port pin.
1: Asynchronous CP1A routed to Port pin.
6 CP1E Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
5 CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0A unavailable at Port pin.
1: Asynchronous CP0A routed to Port pin.
4 CP0E Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3 SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
2 SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
1 SPI0E SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
0 URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
Rev. 1.1
153