C8051F388 Datasheet, PDF (127/285 Pages) –

C8051F388/9/A/B
17.6. PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on
page 269; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 1. The state of the RST pin is unaffected by this reset.
17.7. Flash Error Reset
If a Flash program read, write, or erase operation targets an illegal address, a system reset is generated.
This may occur due to any of the following:
 Programming hardware attempts to write or erase a Flash location which is above the user code space
address limit.
 A Flash read from firmware is attempted above user code space. This occurs when a MOVC operation
is attempted above the user code space address limit.
 A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
 A Flash read, write, or erase attempt is restricted due to a Flash security setting.
 A Flash write or erase is attempted when the V_DD monitor is not enabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
17.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Rev. 1.1
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