C8051F388 Datasheet, PDF (5/285 Pages) –

C8051F388/9/A/B
19. Oscillators and Clock Selection ......................................................................... 136
19.1. System Clock Selection................................................................................. 137
19.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 139
19.2.1. Internal Oscillator Suspend Mode ......................................................... 139
19.3. Clock Multiplier .............................................................................................. 141
19.4. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 142
19.4.1. Calibrating the Internal L-F Oscillator.................................................... 142
19.5. External Oscillator Drive Circuit..................................................................... 143
19.5.1. External Crystal Mode........................................................................... 143
19.5.2. External RC Example............................................................................ 145
19.5.3. External Capacitor Example.................................................................. 145
20. Port Input/Output ................................................................................................. 147
20.1. Priority Crossbar Decoder ............................................................................. 148
20.2. Port I/O Initialization ...................................................................................... 152
20.3. General Purpose Port I/O .............................................................................. 155
21. SMBus0 and SMBus1 (I2C Compatible)............................................................. 166
21.1. Supporting Documents .................................................................................. 167
21.2. SMBus Configuration..................................................................................... 167
21.3. SMBus Operation .......................................................................................... 167
21.3.1. Transmitter Vs. Receiver....................................................................... 168
21.3.2. Arbitration.............................................................................................. 168
21.3.3. Clock Low Extension............................................................................. 168
21.3.4. SCL Low Timeout.................................................................................. 168
21.3.5. SCL High (SMBus Free) Timeout ......................................................... 169
21.4. Using the SMBus........................................................................................... 169
21.4.1. SMBus Configuration Register.............................................................. 169
21.4.2. SMBus Timing Control Register............................................................ 171
21.4.3. SMBnCN Control Register .................................................................... 175
21.4.3.1. Software ACK Generation ............................................................ 175
21.4.3.2. Hardware ACK Generation ........................................................... 175
21.4.4. Hardware Slave Address Recognition .................................................. 178
21.4.5. Data Register ........................................................................................ 182
21.5. SMBus Transfer Modes................................................................................. 184
21.5.1. Write Sequence (Master) ...................................................................... 184
21.5.2. Read Sequence (Master) ...................................................................... 185
21.5.3. Write Sequence (Slave) ........................................................................ 186
21.5.4. Read Sequence (Slave) ........................................................................ 187
21.6. SMBus Status Decoding................................................................................ 187
22. UART0 ................................................................................................................... 193
22.1. Enhanced Baud Rate Generation.................................................................. 194
22.2. Operational Modes ........................................................................................ 195
22.2.1. 8-Bit UART ............................................................................................ 195
22.2.2. 9-Bit UART ............................................................................................ 196
22.3. Multiprocessor Communications ................................................................... 197
23. UART1 ................................................................................................................... 201
Rev. 1.1
5