C8051F388 Datasheet, PDF (120/285 Pages) –

C8051F388/9/A/B
SFR Definition 16.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
3
2
Name
PT5
PT4
PSMB1
Type
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
SFR Address = 0xF7; SFR Page = All Pages
Bit Name
Function
:6 Unused Read = 00b, Write = Don't Care.
5
PT5 Timer 5 Interrupt Priority Control.
This bit sets the priority of the Timer 5 interrupt.
0: Timer 5 interrupt set to low priority level.
1: Timer 5 interrupt set to high priority level.
4
PT4 Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low priority level.
1: Timer 4 interrupt set to high priority level.
3 PSMB1 SMBus1 Interrupt Priority Control.
This bit sets the priority of the SMB1 interrupt.
0: SMB1 interrupt set to low priority level.
1: SMB1 interrupt set to high priority level.
2 Reserved Must Write 0b.
1
PS1 UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupt set to high priority level.
0 PINT2 INT2 Level Interrupt Priority Control.
This bit sets the masking of the INT2 interrupt.
0: INT2 interrupt set to low priority level.
1: INT2 interrupt set to high priority level.
1
0
PS1
PINT2
R/W
R/W
0
0
120
Rev. 1.1