C8051F388 Datasheet, PDF (124/285 Pages) –

C8051F388/9/A/B
17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V_DD settles above
V_RST. A delay occurs before the device is released from reset; the delay decreases as the V_DD ramp time
increases (V_DD ramp time is defined as how fast V_DD ramps from 0 V to V_RST). Figure 17.2. plots the
power-on and V_DD monitor event timing. The maximum V_DD ramp time is 1 ms; slower ramp times may
cause the device to be released from reset before V_DD reaches the V_RST level. For ramp times less than
1 ms, the power-on reset delay (T_PORDelay) is typically less than 0.3 ms.
On exit from a power-on or V_DD monitor reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1.
When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is
cleared by all other resets). Since all resets cause program execution to begin at the same location
(0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The con-
tent of internal data memory should be assumed to be undefined after a power-on reset. The V_DD monitor
is enabled following a power-on reset.
Figure 17.2. Power-On and V_DD Monitor Reset Timing
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Rev. 1.1