C8051F388 Datasheet, PDF (237/285 Pages) –

C8051F388/9/A/B
Figure 25.6. Timer 2 Capture Mode (T2SPLIT = 0)
When T2SPLIT = 1, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A
Timer 2 interrupt is generated if enabled.
Rev. 1.1
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