C8051F388 Datasheet, PDF (104/285 Pages) –

C8051F388/9/A/B
Table 14.1. AC Parameters for External Memory Interface
Parameter
Description
Min*
T_ACS
Address/Control Setup Time
0
T_ACW
Address/Control Pulse Width
1 x T_SYSCLK
T_ACH
Address/Control Hold Time
0
T_ALEH
Address Latch Enable High Time
1 x T_SYSCLK
T_ALEL
Address Latch Enable Low Time
1 x T_SYSCLK
T_WDS
Write Data Setup Time
1 x T_SYSCLK
T_WDH
Write Data Hold Time
0
T_RDS
Read Data Setup Time
20
T_RDH
Read Data Hold Time
0
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Max*
3 x T_SYSCLK
16 x T_SYSCLK
3 x T_SYSCLK
4 x T_SYSCLK
4 x T_SYSCLK
19 x T_SYSCLK
3 x T_SYSCLK
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
104
Rev. 1.1