C8051F388 Datasheet, PDF (9/285 Pages) –

C8051F388/9/A/B
Figure 20.2. Port I/O Cell Block Diagram .............................................................. 148
Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 149
Figure 20.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped) ............................................................................................ 150
Figure 20.5. Crossbar Priority Decoder in Example Configuration
(3 Pins Skipped) ............................................................................................... 151
Figure 21.1. SMBus Block Diagram ...................................................................... 166
Figure 21.2. Typical SMBus Configuration ............................................................ 167
Figure 21.3. SMBus Transaction ........................................................................... 168
Figure 21.4. Typical SMBus SCL Generation ........................................................ 170
Figure 21.5. Typical Master Write Sequence ........................................................ 184
Figure 21.6. Typical Master Read Sequence ........................................................ 185
Figure 21.7. Typical Slave Write Sequence .......................................................... 186
Figure 21.8. Typical Slave Read Sequence .......................................................... 187
Figure 22.1. UART0 Block Diagram ...................................................................... 193
Figure 22.2. UART0 Baud Rate Logic ................................................................... 194
Figure 22.3. UART Interconnect Diagram ............................................................. 195
Figure 22.4. 8-Bit UART Timing Diagram .............................................................. 195
Figure 22.5. 9-Bit UART Timing Diagram .............................................................. 196
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram ......................... 197
Figure 23.1. UART1 Block Diagram ...................................................................... 201
Figure 23.2. UART1 Timing Without Parity or Extra Bit ......................................... 203
Figure 23.3. UART1 Timing With Parity ................................................................ 203
Figure 23.4. UART1 Timing With Extra Bit ............................................................ 203
Figure 23.5. Typical UART Interconnect Diagram ................................................. 204
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 205
Figure 24.1. SPI Block Diagram ............................................................................ 211
Figure 24.2. Multiple-Master Mode Connection Diagram ...................................... 213
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram ........................................................................................ 213
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram ........................................................................................ 214
Figure 24.5. Master Mode Data/Clock Timing ....................................................... 216
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 216
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 217
Figure 24.8. SPI Master Timing (CKPHA = 0) ....................................................... 221
Figure 24.9. SPI Master Timing (CKPHA = 1) ....................................................... 221
Figure 24.10. SPI Slave Timing (CKPHA = 0) ....................................................... 222
Figure 24.11. SPI Slave Timing (CKPHA = 1) ....................................................... 222
Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 228
Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 229
Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 230
Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 235
Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 236
Figure 25.6. Timer 2 Capture Mode (T2SPLIT = 0) ............................................... 237
Rev. 1.1
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