C8051F388 Datasheet, PDF (119/285 Pages) –

C8051F388/9/A/B
SFR Definition 16.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
Name
ET5
ET4
ESMB1
ES1
Type
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
SFR Address = 0xE7; SFR Page = All Pages
Bit Name
Function
7:6 Unused Read = 00b, Write = Don't Care.
5
ET5 Enable Timer 5 Interrupt.
This bit sets the masking of the Timer 5 interrupt.
0: Disable Timer 5 interrupts.
1: Enable interrupt requests generated by the TF5L or TF5H flags.
4
ET4 Enable Timer 4 Interrupt.
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4interrupts.
1: Enable interrupt requests generated by the TF4L or TF4H flags.
3 ESMB1 Enable SMBus1 Interrupt.
This bit sets the masking of the SMB1 interrupt.
0: Disable all SMB1 interrupts.
1: Enable interrupt requests generated by SMB1.
2 Reserved Must Write 0b.
1
ES1 Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
0 EINT2 Enable INT2 Level Interrupt.
This bit sets the masking of the INT2 interrupt.
0: Disable all INT2 interrupts.
1: Enable interrupt requests generated by the INT2 level sense.
0
EINT2
R/W
0
Rev. 1.1
119