C8051F388 Datasheet, PDF (236/285 Pages) –

C8051F388/9/A/B
25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:
T2MH
0
0
1
T2XCLK TMR2H Clock Source
0
SYSCLK / 12
1
External Clock / 8
X
SYSCLK
T2ML
0
0
1
T2XCLK TMR2L Clock Source
0
SYSCLK / 12
1
External Clock / 8
X
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
25.2.3. Timer 2 Capture Modes: LFO Falling Edge
When T2CE = 1, Timer 2 will operate in a special capture mode with the LFO (T2CSS is set to 1). The LFO
falling-edge capture mode can be used to calibrate the internal Low-Frequency Oscillator against the inter-
nal High-Frequency Oscillator or an external clock source. When T2SPLIT = 0, Timer 2 counts up and
overflows from 0xFFFF to 0x0000. Each time a capture event is received, the contents of the Timer 2 reg-
isters (TMR2H:TMR2L) are latched into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2
interrupt is generated if enabled.
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