C8051F388 Datasheet, PDF (91/285 Pages) –

C8051F388/9/A/B
SFR Definition 14.2. EMI0CF: External Memory Interface Configuration
Bit
7
6
5
4
3
2
1
0
Name
Reserved
EMD2
EMD[1:0]
EALE[1:0]
Type
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
1
SFR Address = 0x85; SFR Page = All Pages
Bit
Name
Function
7
Unused Read = 0b; Write = don’t care.
6 Reserved Read = 0b; Must Write 0b.
5
Unused Read = 0b; Write = don’t care.
4
EMD2 EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
3:2 EMD[1:0] EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses
alias to on-chip memory space.
01: Split Mode without Bank Select: Accesses below the on-chip XRAM boundary
are directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the current contents of the Address
High port latches to resolve upper address byte. Note that in order to access
off-chip space, EMI0CN must be set to a page that is not contained in the on-chip
address space.
10: Split Mode with Bank Select: Accesses below the on-chip XRAM boundary are
directed on-chip. Accesses above the on-chip XRAM boundary are directed
off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine
the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visi-
ble to the CPU.
1:0 EALE[1:0] ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 1.1
91