C8051F336_08 Datasheet, PDF (93/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
16.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located in Flash user space offers protection of the Flash program memory from
access (reads, writes, or erases) by unprotected code or the C2 interface. See Section “13. Memory
Organization” on page 74 for the location of the security byte. The Flash security mechanism allows the
user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to 0x01FF), where n is the 1’s
complement number represented by the Security Lock Byte. Note that the page containing the Flash
Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are
‘1’) and locked when any other Flash pages are locked (any bit of the Lock Byte is ‘0’). An example
is shown in Figure 16.1.
Security Lock Byte:
1s Complement:
Flash pages locked:
11111101b
00000010b
3 (First two Flash pages + Lock Byte Page)
Figure 16.1. Security Byte Decoding
Rev.1.0
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