C8051F336_08 Datasheet, PDF (131/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 20.6. P1MAT: Port 1 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P1MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xED
Bit
Name
Function
7:0 P1MAT[7:0] _{Port 1 Match Value.}
Match comparison value used on Port 1 for bits in P1MASK which are set to ‘1’.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
20.6. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to
maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are
returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the
Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the
execution of the read-modify-write instructions that target a Port Latch register as the destination. The
read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL,
INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For
these instructions, the value of the latch register (not the pin) is read, modified, and written back to the
SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to
digital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated
digital functions such as the EMIF should have their PnSKIP bit set to ‘1’.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.4, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
Rev.1.0
131