C8051F336_08 Datasheet, PDF (154/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
21.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. If hardware ACK generation
is disabled, upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The
software must respond to the received slave address with an ACK, or ignore the received slave address
with a NACK. If hardware ACK generation is enabled, the hardware will apply the ACK for a slave address
which matches the criteria set up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK
cycle.
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the
next START is detected. If the received slave address is acknowledged, zero or more data bytes are trans-
mitted. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmit-
ted. The interface enters slave transmitter mode, and transmits one or more bytes of data. After each byte
is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should
be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to
before SI is cleared (an error condition may be generated if SMB0DAT is written following a received
NACK while in slave transmitter mode). The interface exits slave transmitter mode after receiving a STOP.
Note that the interface will switch to slave receiver mode if SMB0DAT is not written following a Slave
Transmitter interrupt. Figure 21.8 shows a typical slave read sequence. Two transmitted data bytes are
shown, though any number of bytes may be transmitted. Notice that all of the “data byte transferred” inter-
rupts occur after the ACK cycle in this mode, regardless of whether hardware ACK generation is enabled.
Interrupts with Hardware ACK Enabled (EHACK = 1)
S
SLA
RA
Data Byte
A
Data Byte
NP
Interrupts with Hardware ACK Disabled (EHACK = 0)
Received by SMBus
Interface
Transmitted by
SMBus Interface
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Figure 21.8. Typical Slave Read Sequence
21.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. The appropriate actions to
take in response to an SMBus event depend on whether hardware slave address recognition and ACK
generation is enabled or disabled. Table 21.5 describes the typical actions when hardware slave address
recognition and ACK generation is disabled. Table 21.6 describes the typical actions when hardware slave
address recognition and ACK generation is enabled. In the tables, STATUS VECTOR refers to the four
upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typ-
ical responses; application-specific procedures are allowed as long as they conform to the SMBus specifi-
cation. Highlighted responses are allowed by hardware but do not conform to the SMBus specification.
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