C8051F336_08 Datasheet, PDF (132/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 20.7. P0: Port 0
Bit
7
6
5
4
3
2
1
0
Name
P0[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0x80; Bit Addressable
Bit Name
Description
7:0 P0[7:0] _{Port 0 Data.}
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Write
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Read
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
SFR Definition 20.8. P0MDIN: Port 0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF1
Bit
Name
7:0 P0MDIN[7:0]
Function
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
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Rev.1.0