C8051F336_08 Datasheet, PDF (125/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Figure 20.5 shows an example of the resulting pin assignments of the device with UART0, SMBus, and
CEX0 enabled, the XTAL1 (P0.2) and XTAL2 (P0.3) pins skipped (P0SKIP = 0x0C). UART0 is the highest
priority and it will be assigned first. The UART can only appear on P0.4 and P0.5, so that is where it is
assigned. The next-highest enabled peripheral is the SMBus. P0.0 and P0.1 are free, so the SMBus takes
these two pins. The last peripheral enabled is the PCA’s CEX0 pin. P0.0, P0.1, P0.4 and P0.5 are already
occupied by higher-priority peripherals. Additionally, P0.2 and P0.3 are set to be skipped by the crossbar.
The CEX0 signal ends up getting routed to P0.6, as it is the next available pin. The other pins on the
device are available for use as general-purpose digital I/O or analog functions.
P0
P1
P2
SF Signals VREF IDA x1 x2
CNVSTR
PIN I/O
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1² 2² 3² 4²
TX0
RX0
SCK
MISO
MOSI
NSS¹
SDA
SCL
CP0
CP0A
SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
00110000000000000000
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:3]
SF Signals
Port pin potentially available to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
Notes:
1. NSS is only pinned out in 4-wire SPI Mode
2. Pins P2.1-P2.4 only on QFN24 Package
3. Pin 2.0 unavailable on crossbar in QFN20 Package
Figure 20.5. Crossbar Priority Decoder Example
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
Rev.1.0
125