C8051F336_08 Datasheet, PDF (176/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 23.3. SPI0CKR: SPI0 Clock Rate
Bit
7
6
5
4
3
2
1
0
Name
SCR[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA2
Bit
Name
Function
7:0 SCR[7:0] _{SPI0 Clock Rate.}
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
f_SCK = _2-----×-----₍--S----P---SI--0-Y--C--S--K--C--R--L--[-K-7---:--0---]---+-----1----₎
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f_SCK = _2---2--×-0---0-₍--40---0--+-0---0-1---₎
f_SCK = 200kHz
SFR Definition 23.4. SPI0DAT: SPI0 Data
Bit
7
6
5
4
3
2
1
0
Name
SPI0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA3
Bit
Name
Function
7:0 SPI0DAT[7:0] _{SPI0 Transmit and Receive Data.}
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
176
Rev.1.0