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C8051F336_08 Datasheet, PDF (103/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU | |||
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C8051F336/7/8/9
SFR Definition 17.1. VDM0CN: VDD Monitor Control
Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT
Type R/W
R
R
R
R
R
R
R
Reset Varies
Varies
0
0
0
0
0
0
SFR Address = 0xFF
Bit
Name
Function
7
VDMEN VDD Monitor Enable.
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 17.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6
VDDSTAT VDD Status.
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
5:0 UNUSED Unused. Read = 000000b; Write = Donât care.
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section â6. Electrical Characteris-
ticsâ on page 27 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an
external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read â1â, signifying the MCD as the reset source; otherwise,
this bit reads â0â. Writing a â1â to the MCDRSF bit enables the Missing Clock Detector; writing a â0â disables
it. The state of the RST pin is unaffected by this reset.
Rev.1.0
103
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