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C8051F336_08 Datasheet, PDF (119/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU
C8051F336/7/8/9
20. Port Input/Output
Digital and analog resources are available through 17 (C8051F336/7) or 21 (C8051F338/9) I/O pins. Port
pins P0.0-P2.3 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources, or assigned to an analog function as shown in Figure 20.4. Port pin P2.4 on the C8051F338/9
and P2.0 on the C8051F336/7 can be used as GPIO and are shared with the C2 Interface Data signal
(C2D). The designer has complete control over which functions are assigned, limited only by the number of
physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-
less of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.4 and Figure 20.5). The registers XBR0 and XBR1, defined in SFR Definition 20.1 and SFR
Definition 20.2, are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Section “6. Electrical Characteristics” on page 27.
XBR0, XBR1,
PnSKIP Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Highest
Priority
Lowest
Priority
2
UART
Priority
Decoder
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
4
SPI
2
SMBus
CP0
2
Outputs
P0.0
Digital
P0
Crossbar 8
I/O
Cells
P0.7
SYSCLK
PCA
4
2
T0, T1
P1.0
8
P1
I/O
Cells
P1.7
8
P0 (P0.0-P0.7)
8
P1 (P1.0-P1.7)
4
P2
I/O
Cell
P2.0*
P2.3*
4
P2 (P2.0-P2.3*)
To Analog Peripherals
(ADC0, CP0, VREF, XTAL)
*P2.0-P2.3 are only available through
the crossbar on QFN24 Packages.
Figure 20.1. Port I/O Functional Block Diagram
Rev.1.0
119