C8051F336_08 Datasheet, PDF (121/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
WEAKPUD
(Weak Pull-Up Disable)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDIN.x
(1 for digital)
(0 for analog)
To/From Analog
Peripheral
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
VDD
VDD
(WEAK)
PORT
PAD
GND
Figure 20.2. Port I/O Cell Block Diagram
20.1.3. Interfacing Port I/O to 5V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than VDD and less than 5.25V. An external pull-up resistor to the higher supply
voltage is typically required for most systems.
Important Note: In a multi-voltage interface, the external pull-up resistor should be sized to allow a current
of at least 150uA to flow into the Port pin when the supply voltage is between (VDD + 0.6V) and
(VDD + 1.0V). Once the Port pin voltage increases beyond this range, the current flowing into the Port pin
is minimal. Figure 20.3 shows the input current characteristics of port pins driven above VDD. The port pin
requires 150 µA peak overdrive current when its voltage reaches approximately (VDD + 0.7 V).
V_DD
I/O
Cell
I_Vtest
+_-
V_test
0
I_Vtest ^-10
(µA)
-150
V_test (V)
V_DD V_DD+0.7
Port I/O Overdrive Test Circuit
Port I/O Overdrive Current vs. Voltage
Figure 20.3. Port I/O Overdrive Current
Rev.1.0
121