C8051F336_08 Datasheet, PDF (112/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 19.3. OSCICN: Internal H-F Oscillator Control
Bit
7
6
5
4
3
2
1
0
Name ^{IOSCEN IFRDY SUSPEND STSYNC}
IFCN[1:0]
Type ^R/W
R
R/W
R
R
R
R/W
Reset
1
1
0
0
0
0
0
0
SFR Address = 0xB2
Bit Name
Function
7 IOSCEN _{Internal H-F Oscillator Enable Bit.}
0: Internal H-F Oscillator Disabled.
1: Internal H-F Oscillator Enabled.
6
IFRDY _{Internal H-F Oscillator Frequency Ready Flag.}
0: Internal H-F Oscillator is not running at programmed frequency.
1: Internal H-F Oscillator is running at programmed frequency.
5 SUSPEND _{Internal Oscillator Suspend Enable Bit.}
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
4 STSYNC _{Suspend Timer Synchronization Bit.}
This bit is used to indicate when it is safe to read and write the registers associated
with the suspend wake-up timer. If a suspend wake-up source other than the timer
has brought the oscillator out of suspend mode, it may take up to three timer clocks
before the timer can be read or written. When STSYNC reads '1', reads and writes of
the timer register should not be performed. When STSYNC reads '0', it is safe to
read and write the timer registers.
3:2 Unused Unused. Read = 00b; Write = Don’t Care
1:0 IFCN[1:0] _{Internal H-F Oscillator Frequency Divider Control Bits.}
00: SYSCLK derived from Internal H-F Oscillator divided by 8.
01: SYSCLK derived from Internal H-F Oscillator divided by 4.
10: SYSCLK derived from Internal H-F Oscillator divided by 2.
11: SYSCLK derived from Internal H-F Oscillator divided by 1.
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Rev.1.0