C8051F336_08 Datasheet, PDF (19/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F336/7/8/9
Name
V_DD
GND
Pin
’F336/7
3
2
RST/
4
C2CK
C2D
5
P0.0/
1
VREF
P0.1
20
IDA0
P0.2/
19
XTAL1
P0.3/
18
XTAL2
P0.4
17
P0.5
16
P0.6/
15
CNVSTR
Pin
Type Description
’F338/9
4
Power Supply Voltage.
3
Ground.
This ground connection is required. The center pad may
optionally be connected to ground also.
5
D I/O Device Reset. Open-drain output of internal POR or V_DD
monitor. An external source can initiate a system reset by
driving this pin low for at least 10 µs.
D I/O Clock signal for the C2 Debug Interface.
6
D I/O Bi-directional data signal for the C2 Debug Interface.
Shared with P2.0 on 20-pin packaging and P2.4 on 24-pin
packaging.
2
D I/O or Port 0.0.
A In
A In External VREF input.
1
D I/O or Port 0.1.
A In
A Out IDA0 Output.
24 D I/O or Port 0.2.
A In
A In External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
23 D I/O or Port 0.3.
A In
A I/O or External Clock Output. For an external crystal or resonator,
D In ^{this pin is the excitation driver. This pin is the external clock}
input for CMOS, capacitor, or RC oscillator configurations.
22 D I/O or Port 0.4.
A In
21 D I/O or Port 0.5.
A In
20 D I/O or Port 0.6.
A In
D In ADC0 External Convert Start or IDA0 Update Source Input.
Rev.1.0
19