C8051F336_08 Datasheet, PDF (110/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
Name
CLKSL[1:0]
Type
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA9
Bit Name
Function
7:2 UNUSED Unused. Read = 000000b; Write = Don’t Care
1:0 CLKSL[1:0] _{System Clock Source Select Bits.}
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the
IFCN bits in register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the
OSCLD bits in register OSCLCN.
11: reserved.
110
Rev.1.0