C8051F336_08 Datasheet, PDF (136/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 20.15. P2: Port 2
Bit
7
6
5
4
3
2
1
0
Name
P2[4:0]
Type
R
R
R
R/W
Reset
0
0
0
1
1
1
1
1
SFR Address = 0xA0; Bit Addressable
Bit Name
Description
Write
Read
7:5 UNUSED _Unused.
Don’t Care
000b
4:0 P2[4:0] _{Port 2 Data.}
0: Set output latch to logic 0: P2.n Port pin is logic
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
LOW.
LOW.
1: Set output latch to logic 1: P2.n Port pin is logic
HIGH.
HIGH.
figured for digital I/O.
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
SFR Definition 20.16. P2MDIN: Port 2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDIN[7:0]
Type
R
R
R
R
R/W
Reset
0
0
0
0
1
1
1
1
SFR Address = 0xF3
Bit
Name
Function
7:4 UNUSED Unused. Read = 0000b; Write = Don’t Care
3:0 P2MDIN[3:0] _{Analog Configuration Bits for P2.3–P2.0 (respectively).}
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.
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Rev.1.0