C8051F336_08 Datasheet, PDF (87/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 15.3. EIE1: Extended Interrupt Enable 1
Bit
7
Name ^ET3
Type ^R/W
Reset
0
6
Reserved
R/W
0
5
ECP0
R/W
0
4
EPCA0
R/W
0
3
EADC0
R/W
0
2
EWADC0
R/W
0
1
EMAT
R/W
0
0
ESMB0
R/W
0
SFR Address = 0xE6
Bit Name
Function
7
ET3 _{Enable Timer 3 Interrupt.}
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
6 Reserved Reserved. Must Write 0.
5 ECP0 _{Enable Comparator0 (CP0) Interrupt.}
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4 EPCA0 _{Enable Programmable Counter Array (PCA0) Interrupt.}
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
3 EADC0 _{Enable ADC0 Conversion Complete Interrupt.}
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
2 EWADC0 _{Enable Window Comparison ADC0 Interrupt.}
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
1 EMAT _{Enable Port Match Interrupts.}
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0 ESMB0 _{Enable SMBus (SMB0) Interrupt.}
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Rev.1.0
87