C8051F336_08 Datasheet, PDF (105/227 Pages) Silicon Laboratories – Mixed-Signal Byte-Programmable EPROM MCU

C8051F336/7/8/9
SFR Definition 17.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
Name
FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF
Type
R
R
R/W
R/W
R
R/W
R/W
R
Reset
0
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xEF
Bit Name
Description
Write
Read
7 UNUSED _Unused.
Don’t care.
0
6 FERROR _{Flash Error Reset Flag.}
N/A
Set to ‘1’ if Flash
read/write/erase error
caused the last reset.
5 C0RSEF _{Comparator0 Reset Enable} Writing a ‘1’ enables
and Flag.
Comparator0 as a reset
source (active-low).
Set to ‘1’ if Comparator0
caused the last reset.
4 SWRSF _{Software Reset Force and} Writing a ‘1’ forces a sys- Set to ‘1’ if last reset was
Flag.
tem reset.
caused by a write to
SWRSF.
3 WDTRSF _{Watchdog Timer Reset Flag.} N/A
Set to ‘1’ if Watchdog
Timer overflow caused the
last reset.
2 MCDRSF _{Missing Clock Detector}
Enable and Flag.
Writing a ‘1’ enables the Set to ‘1’ if Missing Clock
Missing Clock Detector. Detector timeout caused
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1 PORSF _{Power-On / VDD Monitor}
Writing a ‘1’ enables the Set to ‘1’ anytime a power-
Reset Flag, and V_DD monitor
Reset Enable.
V_DD monitor as a reset
source.
on or V_DD monitor reset
occurs.
Writing ‘1’ to this bit
When set to ‘1’ all other
before the V_DD monitor RSTSRC flags are inde-
is enabled and stabilized terminate.
may cause a system
reset.
0 PINRSF _{HW Pin Reset Flag.}
N/A
Set to ‘1’ if RST pin
caused the last reset.
Note: Do not use read-modify-write operations on this register
Rev.1.0
105