SI5328 Datasheet, PDF (9/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Table 3. AC Characteristics
(V_DD = 2.5 ±10% or 3.3 V ±10%, T_A = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XA_RIN RATE[1:0] = LM, ML, MH,
—
12
—
k
ac coupled
Input Voltage Swing
XA_VPP RATE[1:0] = LM, ML, MH,
0.5
—
1.2
V_PP
ac coupled
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing XA/XB_VPP RATE[1:0] = LM, ML, MH
0.5
—
1.2
V_PP,
each.
CKINn Input Pins
Input Frequency
CKN_F
0.008
—
710
MHz
Input Duty Cycle
(Minimum Pulse
Width)
CKN_DC Input frequency > 225 MHz
40
—
60
%
Input frequency < 225 MHz
2
—
—
ns
refers to both high and low
widths
Input Capacitance
CKN_CIN
—
—
3
pF
Input Rise/Fall Time
CKN_TRF
20–80%
See Figure 2
—
—
11
ns
CKOUTn Output Pins
(See ordering section for speed grade vs frequency limits)
Output Frequency
(Output not config-
ured for CMOS)
Maximum Output
Frequency in CMOS
Format
CKO_F
CKO_F
N1  6
0.008
—
808
MHz
—
—
212.5
MHz
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKO_TRF
CMOS Output
V_DD = 2.25
C_LOAD = 5 pF
—
—
8
ns
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKO_TRF
CMOS Output
V_DD = 2.97
C_LOAD = 5 pF
—
—
2
ns
Notes:
1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for
further details.
2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details.
Rev. 1.0
9