SI5328 Datasheet, PDF (30/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 10.
Bit
D7
Name
Type
D6
D5
Reserved
R
D4
D3
D2
D1
D0
DSBL2_REG DSBL1_REG Reserved Reserved
R/W
R/W
R
R
Reset value = 0000 0000
Bit
Name
Function
7:4 Reserved Reserved.
3 DSBL2_REG DSBL2_REG.
This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is
selected, the N2_LS output divider is also powered down.
0: CKOUT2 enabled
1: CKOUT2 disabled
2 DSBL1_REG DSBL1_REG.
This bit controls the powerdown of the CKOUT1 output buffer. If disable mode is
selected, the N1_LS output divider is also powered down.
0: CKOUT1 enabled
1: CKOUT1 disabled
1:0 Reserved Reserved.
30
Rev. 1.0