SI5328 Datasheet, PDF (27/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 6.
Bit
Name
Type
D7
Reserved
R
D6
SLEEP
R/W
D5
D4
D3
SFOUT2_REG [2:0]
R/W
D2
D1
D0
SFOUT1_REG [2:0]
R/W
Reset value = 0010 1101
Bit
Name
Function
7
Reserved
Reserved.
6
SLEEP
SLEEP.
In sleep mode, all clock outputs are disabled and the maximum amount of internal
circuitry is powered down to reduce power dissipation and noise generation. This
bit overrides the SFOUTn_REG[2:0] output signal format settings.
0: Normal operation
1: Sleep mode
5:3 SFOUT2_REG [2:0] SFOUT2_REG [2:0].
Controls output signal format and disable for CKOUT2 output buffer.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
110: CML
111: LVDS
2:0 SFOUT1_REG [2:0] SFOUT1_REG [2:0].
Controls output signal format and disable for CKOUT1 output buffer.
000: Reserved
001: Disable
010: CMOS (Bypass mode not supported)
011: Low swing LVDS
100: Reserved
101: LVPECL
111: LVDS
Rev. 1.0
27