SI5328 Datasheet, PDF (34/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 21.
Bit
D7
D6
Name Reserved
Type
R
Force 1
D5
D4
D3
Reserved
R
R
R
D2
D1
D0
CK1_ACTV_PIN CKSEL_ PIN
R
R/W
R/W
Reset value = 1111 1111
Bit
Name
Function
7:2
Reserved Reserved.
1 CK1_ACTV_PIN CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin
controlled clock selection is not being used. (See CKSEL_PIN)
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
0
CKSEL_PIN CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
34
Rev. 1.0