SI5328 Datasheet, PDF (33/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 20.
Bit
D7
Name
Type
D6
D5
Reserved
R
D4
D3
D2
D1
D0
CK2_BAD_PIN CK1_BAD_PIN LOL_PIN INT_PIN
R/W
R/W
R/W
R/W
Reset value = 0011 1110
Bit
Name
Function
7:4
Reserved Reserved.
3 CK2_BAD_PIN CK2_BAD_PIN.
The CK2_BAD status can be reflected on the C2B output pin.
0: C2B output pin tristated
1: C2B status reflected to output pin
2 CK1_BAD_PIN CK1_BAD_PIN.
Either LOS1 or INT (see INT_PIN) status can be reflected on the INT_C1B output pin.
0: INT_C1B output pin tristated
1: LOS1 or INT (see INT_PIN) status reflected to output pin
1
LOL_PIN LOL_PIN.
The LOL_INT status bit can be reflected on the LOL output pin.
0: LOL output pin tristated
1: LOL_INT status reflected to output pin
0
INT_PIN INT_PIN.
Reflects the interrupt status on the INT_C1B output pin.
0: Interrupt status not displayed on INT_C1B output pin. Instead, the INT_C1B pin
indicates when CKIN1 is bad. If CK1_BAD_PIN = 0, INT_C1B output pin is tristated.
1: Interrupt status reflected to output pin.
Rev. 1.0
33