SI5328 Datasheet, PDF (43/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 41.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
N2_LS [15:8]
Type
R/W
Reset value = 0000 0000
Bit
Name
Function
7:0 N2_LS [15:8] N2_LS [15:8].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 2²⁰
Valid divider values = [2, 4, 6, ..., 2²⁰]
Register 42.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
N2_LS [7:0]
Type
R/W
Reset value = 1111 1001
Bit
Name
Function
7:0 N2_LS [7:0] N2_LS [7:0].
Sets value for N2 low-speed divider, which drives phase detector.
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111 = 2²⁰
Valid divider values = [2, 4, 6, ..., 2²⁰]
Rev. 1.0
43