SI5328 Datasheet, PDF (21/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the
specified Reset Values may result in undefined device behavior. Registers not listed, such as Register 64, should never be written to.
Register
0
1
2
3
4
5
6
7
8
9
10
11
19
20
21
22
23
24
25
31
32
33
34
D7
D6
D5
D4
D3
D2
D1
D0
FREE_RUN CKOUT_ALWAYS_ON
BYPASS_REG
CK_PRIOR2[1:0]
CK_PRIOR[1:0]
BWSEL_REG[3:0]
CKSEL_REG[1:0]
DHOLD
SQ_ICAL
AUTOSEL_REG[1:0]
HST_DEL[4:0]
ICMOS[1:0]
SLEEP
SFOUT2_REG[2:0]
SFOUT1_REG[2:0]
FOSREFSEL[2:0]
HLOG_2[1:0]
HLOG_1[1:0]
HIST_AVG[4:0]
DSBL2_ REG DSBL1_ REG
PD_CK2
PD_CK1
FOS_EN
FOS_THR[1:0]
VALTIME[1:0]
LOCK[T2:0]
CK2_BAD_PIN CK1_ BAD_ PIN
LOL_PIN
INT_PIN
CK1_ACTV_PIN
CKSEL_PIN
CK_ACTV_ POL CK_BAD_ POL
LOL_POL
INT_POL
LOS2_MSK
LOS1_MSK
LOSX_MSK
FOS2_MSK
FOS1_MSK
LOL_MSK
N1_HS[2:0]
NC1_LS[19:16]
NC1_LS[15:8]
NC1_LS[7:0]
NC2_LS[19:16]
Rev. 1.0
21