SI5328 Datasheet, PDF (24/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 1.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
CK_PRIOR2 [1:0]
CK_PRIOR1 [1:0]
Type
R
R/W
R/W
Reset value = 1110 0100
Bit
Name
Function
7:4
Reserved Reserved.
3:2 CK_PRIOR2 [1:0] CK_PRIOR 2.
Selects which of the input clocks will be 2nd priority in the autoselection state
machine.
00: CKIN1 is 2nd priority.
01: CKIN2 is 2nd priority.
10: Reserved
11: Reserved
1:0 CK_PRIOR1 [1:0] CK_PRIOR 1.
Selects which of the input clocks will be 1st priority in the autoselection state
machine.
00: CKIN1 is 1st priority.
01: CKIN2 is 1st priority.
10: Reserved
11: Reserved
Register 2.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
BWSEL_REG [3:0]
Reserved
Type
R/W
R
Reset value = 0100 0010
Bit
Name
Function
7:4 BWSEL_REG [3:0] BWSEL_REG.
Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After
BWSEL_REG is written with a new value, an ICAL is required for the change to
take effect.
3:0
Reserved
Reserved.
24
Rev. 1.0