SI5328 Datasheet, PDF (26/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 4.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name AUTOSEL_REG [1:0] Reserved
HIST_DEL [4:0]
Type
R/W
R
R/W
Reset value = 0001 0010
Bit
Name
Function
7:6 AUTOSEL_REG [1:0] AUTOSEL_REG [1:0].
Selects method of input clock selection to be used.
00: Manual (either register or pin controlled, see CKSEL_PIN)
01: Automatic Non-Revertive
10: Automatic Revertive
11: Reserved
See the Si53xx Family Reference Manual for a detailed description.
5
Reserved
Reserved.
4:0
HIST_DEL [4:0] HIST_DEL [4:0].
Selects amount of delay to be used in generating the history information used for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description.
Register 5.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
ICMOS [1:0]
Reserved
Type
R/W
R
Reset value = 1110 1101
Bit
Name
Function
7:6 ICMOS [1:0] ICMOS [1:0].
When the output buffer is set to CMOS mode, these bits determine the output buffer drive
strength. The first number below refers to 3.3 V operation; the second to 2.5 V operation.
These values assume CKOUT+ is tied to CKOUT–.
00: 8 mA/5 mA
01: 16 mA/10 mA
10: 24 mA/15 mA
11: 32 mA/20 mA
5:0 Reserved Reserved.
26
Rev. 1.0