SI5328 Datasheet, PDF (60/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Pin # Pin Name I/O Signal Level
Description
18
LOL
O LVCMOS PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked
1 = PLL unlocked
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
21
CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.
Input: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-
tion and this input tristates. If configured for input, must be tied high
or low.
Output: In automatic clock selection mode, this pin indicates which
of the two input clocks is currently the active clock. If alarms exist on
both clocks, CK_ACTV will indicate the last active clock that was
used before entering the digital hold state. The CK_ACTV_PIN reg-
ister bit must be set to 1 to reflect the active clock status to the
CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status will
always be reflected in the CK_ACTV_REG read only register bit.
22
SCL
I
LVCMOS Serial Clock.
This pin functions as the serial clock input for both SPI and I²C
modes.
This pin has a weak pull-down.
23 SDA_SDO I/O LVCMOS Serial Data.
In I²C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial
data output.
25
A1
I
LVCMOS Serial Port Address.
24
A0
In I²C control mode (CMODE = 0), these pins function as hardware
controlled address bits. The I²C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
60
Rev. 1.0