SI5328 Datasheet, PDF (18/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
VDD = 3.3 V
System
Power
Supply
130 
130 
C₄
C₁
Ferrite
Bead _C2
C₃
82 
82 
CKIN1+
CKIN1–
1 µF
0.1 µF
0.1 µF
0.1 µF
CKOUT1+
CKOUT1–
Input
Clock
Sources*
VDD = 3.3 V
130 
82 
130 
CKIN2+
82 
CKIN2–
CKOUT2+
CKOUT2–
Si5328
INT_C1B
C2B
0.1 µF
+
100 
–
0.1 µF
0.1 µF
+
100 
–
0.1 µF
Clock Outputs
Interrupt/CLKIN1 Invalid Indicator
CLKIN2 Invalid Indicator
VDD
15 k
Ref Clk Rate
15 k
RATE[1:0]²
Refclk+
Refclk–
0.1 µF
XA
0.1 µF
XB
Control Mode (H)
Reset
CMODE
RST
LOL
SS
SDO
SDI
SCLK
CS_CA
PLL Loss of Lock Indicator
Slave Select
Serial Data Out
Serial Data In
SPI Interface
Serial Clock
Clock Select/Clock Active
Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2),
and H (VDD).
Figure 5. Si5328 Typical Application Circuit (SPI Control Mode)
18
Rev. 1.0