SI5328 Datasheet, PDF (50/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 130.
Bit
Name
Type
D7
Reserved
R
D6
DIGHOLDVALID
R
D5
D4
D3
Reserved
R
D2
D1
FOS2_INT FOS1_INT
R
R
D0
LOL_INT
R
Reset value = 0000 0001
Bit
Name
Function
7
Reserved
Reserved.
6 DIGHOLDVALID Digital Hold Valid.
Indicates if the digital hold circuit has enough samples of a valid clock to meet digital
hold specifications.
0: Indicates digital hold history registers have not been filled. The digital hold output
frequency may not meet specifications.
1: Indicates digital hold history registers have been filled. The digital hold output
frequency is valid.
5:3
Reserved
Reserved.
2
FOS2_INT CKIN2 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN2 input.
1
FOS1_INT CKIN1 Frequency Offset Status.
0: Normal operation.
1: Internal frequency offset alarm on CKIN1 input.
0
LOL_INT
PLL Loss of Lock Status.
0: PLL locked.
1: PLL unlocked.
50
Rev. 1.0