SI5328 Datasheet, PDF (38/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 25.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
N1_HS [2:0]
Reserved
Type
R/W
R
Reset value = 0010 0000
Bit
Name
Function
7:5 N1_HS [2:0] N1_HS [2:0].
Sets value for N1 high speed divider which drives NCn_LS (n = 1 to 2) low-speed divider.
000: N1 = 4
001: N1 = 5
010: N1 = 6
011: N1 = 7
100: N1 = 8
101: N1 = 9
110: N1 = 10
111: N1 = 11
4:0 Reserved Reserved.
Register 31.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Reserved
NC1_LS [19:16]
Type
R
R/W
Reset value = 0000 0000
Bit
Name
Function
7:4
Reserved Reserved.
3:0 NC1_LS [19:16] NC1_LS [19:16].
Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must be 0 or
odd.
00000000000000000000 = 1
00000000000000000001 = 2
00000000000000000011 = 4
00000000000000000101 = 6
...
11111111111111111111=2²⁰
Valid divider values=[1, 2, 4, 6, ..., 2²⁰]
38
Rev. 1.0