SI5328 Datasheet, PDF(6/70 Page) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

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SI5328 Datasheet, PDF (6/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

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Si5328

Table 2. DC Characteristics (Continued)

(VDD = 2.5 V Â±10% or 3.3 V Â±10%, TA = â40 to 85 Â°C)

Parameter

Symbol

Test Condition

Output Clocks (CKOUTn)

Min

Typ

Max

Unit

Common Mode

CKOVCM LVPECL 100 ï load line- VDD â1.42

to-line

VDD â1.25

Differential Output

CKOVD LVPECL 100 ï load line-

1.1

1.9

Swing3

to-line

Single Ended Output CKOVSE LVPECL 100 ï load line-

0.5

Swing3

to-line

0.93

Differential Output

Voltage3

CKOVD CML 100 ï load line-to-

350

line

425

500

Common Mode Output CKOVCM CML 100 ï load line-to-

VDDâ0.36

Voltage3

line

Differential Output

CKOVD

LVDS

500

700

900

Voltage3

100 ï load line-to-line

Low Swing LVDS

350

425

500

100 ï load line-to-line

Common Mode Output CKOVCM LVDS 100 ïï load line-to- 1.125

1.2

Voltage3

line

1.275

Differential Output

CKORD

CML, LVPECL, LVDS

200

Resistance

Output Voltage Low CKOVOLLH

CMOS

0.4

VPP

mVPP

Output Voltage High CKOVOHLH

VDD = 2.25 V

CMOS

0.8 x VDD

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

Rev. 1.0

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