SI5328 Datasheet, PDF (35/70 Pages) Silicon Laboratories – ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Si5328
Register 22.
Bit
D7
Name
Type
D6
D5
Reserved
R
D4
D3
D2
D1
D0
CK_ACTV_POL CK_BAD_ POL LOL_POL INT_POL
R/W
R/W
R/W
R/W
Reset value = 1101 1111
Bit
Name
Function
7:4
Reserved Reserved.
3 CK_ACTV_ POL CK_ACTV_POL.
Sets the active polarity for the CS_CA signals when reflected on an output pin.
0: Active low
1: Active high
2 CK_BAD_ POL CK_BAD_POL.
Sets the active polarity for the INT_C1B and C2B signals when reflected on output
pins.
0: Active low
1: Active high
1
LOL_POL LOL_POL.
Sets the active polarity for the LOL status when reflected on an output pin.
0: Active low
1: Active high
0
INT_POL INT_POL.
Sets the active polarity for the interrupt status when reflected on the INT_C1B output
pin.
0: Active low
1: Active high
Rev. 1.0
35